The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2009
Filed:
Oct. 17, 2007
Richard A. Conti, Katohah, NY (US);
Ronald P. Bourque, Wappingers Falls, NY (US);
Nancy R. Klymko, Hopewell Junction, NY (US);
Anita Madan, Danbury, NY (US);
Michael C. Smits, Poughkeepsie, NY (US);
Roy H. Tilghman, Stormville, NY (US);
Kwong Hon Wong, Wappingers Falls, NY (US);
Daewon Yang, Hopewell Junction, NY (US);
Richard A. Conti, Katohah, NY (US);
Ronald P. Bourque, Wappingers Falls, NY (US);
Nancy R. Klymko, Hopewell Junction, NY (US);
Anita Madan, Danbury, NY (US);
Michael C. Smits, Poughkeepsie, NY (US);
Roy H. Tilghman, Stormville, NY (US);
Kwong Hon Wong, Wappingers Falls, NY (US);
Daewon Yang, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Novellus Systems. Inc., San Jose, CA (US);
Abstract
A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.