The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2007
Filed:
Dec. 19, 2003
Justin K. Brask, Portland, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Jack Kavalieros, Portland, OR (US);
Uday Shah, Portland, OR (US);
Matthew V. Metz, Hillsboro, OR (US);
Chris E. Barns, Portland, OR (US);
Suman Datta, Beaverton, OR (US);
Christopher D. Thomas, Aloha, OR (US);
Robert S. Chau, Beaverton, OR (US);
Justin K. Brask, Portland, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Jack Kavalieros, Portland, OR (US);
Uday Shah, Portland, OR (US);
Matthew V. Metz, Hillsboro, OR (US);
Chris E. Barns, Portland, OR (US);
Suman Datta, Beaverton, OR (US);
Christopher D. Thomas, Aloha, OR (US);
Robert S. Chau, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.