The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Nov. 02, 2004
Shiann-tsong Tsai, Hsinchu, TW;
Yu-ming Hsu, Hsinchu, TW;
Wen-lung Wu, Hsinchu, TW;
Kuen-huang Chen, Hsinchu, TW;
Wen-sheng Su, Hsinchu, TW;
Chin-hsing Lin, Hsinchu, TW;
Shiann-Tsong Tsai, Hsinchu, TW;
Yu-Ming Hsu, Hsinchu, TW;
Wen-Lung Wu, Hsinchu, TW;
Kuen-Huang Chen, Hsinchu, TW;
Wen-Sheng Su, Hsinchu, TW;
Chin-Hsing Lin, Hsinchu, TW;
UltraTera Corporation, , TW;
Abstract
A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated package products.