The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2006
Filed:
Oct. 31, 2002
Hans-georg Fröhlich, Dresden, DE;
Johannes Kowalewski, Dresden, DE;
Udo Götschkes, Dresden, DE;
Frank Hübinger, Dresden, DE;
Gerd Krause, Dresden, DE;
Heike Langnickel, Wachau, DE;
Antje Lässig, Dresden, DE;
Reiner Trinowitz, Dresden, DE;
Hans-Georg Fröhlich, Dresden, DE;
Johannes Kowalewski, Dresden, DE;
Udo Götschkes, Dresden, DE;
Frank Hübinger, Dresden, DE;
Gerd Krause, Dresden, DE;
Heike Langnickel, Wachau, DE;
Antje Lässig, Dresden, DE;
Reiner Trinowitz, Dresden, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in layers on a substrate during lithographic exposure, in particular, in the case of a wafer during the production of DRAMs, includes a mark structure, and at least one layer of a definable thickness underneath the mark structure for adjusting the physical position of the mark structure relative to a reference plane in or on the substrate. Also provided is a wafer having such a configuration and a process for providing such a configuration. The invention allows a mark configuration to have mark structures exhibiting good contrast regardless of the design or the process conditions.