The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2005
Filed:
Jul. 18, 2002
Brian E. Stine, Los Altos Hills, CA (US);
Christopher Hess, San Ramon, CA (US);
John Kibarian, Los Altos Hills, CA (US);
Kimon Michaels, San Jose, CA (US);
Joseph C. Davis, Allen, TX (US);
Purnendu K. Mozumder, Plano, TX (US);
Sherry F. Lee, San Jose, CA (US);
Larg H. Weiland, San Ramon, CA (US);
Dennis J. Ciplickas, San Jose, CA (US);
David M. Stashower, Los Gatos, CA (US);
Brian E. Stine, Los Altos Hills, CA (US);
Christopher Hess, San Ramon, CA (US);
John Kibarian, Los Altos Hills, CA (US);
Kimon Michaels, San Jose, CA (US);
Joseph C. Davis, Allen, TX (US);
Purnendu K. Mozumder, Plano, TX (US);
Sherry F. Lee, San Jose, CA (US);
Larg H. Weiland, San Ramon, CA (US);
Dennis J. Ciplickas, San Jose, CA (US);
David M. Stashower, Los Gatos, CA (US);
PDF Solutions, Inc., San Jose, CA (US);
Abstract
A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.