The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Dec. 21, 2022
Intel Corporation, Santa Clara, CA (US);
Bohan Shan, Chandler, AZ (US);
Haobo Chen, Chandler, AZ (US);
Yiqun Bai, Chandler, AZ (US);
Dingying Xu, Chandler, AZ (US);
Srinivas Venkata Ramanuja Pietambaram, Chandler, AZ (US);
Hongxia Feng, Chandler, AZ (US);
Gang Duan, Chandler, AZ (US);
Xiaoying Guo, Chandler, AZ (US);
Ziyin Lin, Chandler, AZ (US);
Bai Nie, Chandler, AZ (US);
Kyle Jordan Arrington, Gilbert, AZ (US);
Jeremy D. Ecton, Gilbert, AZ (US);
Brandon C. Marin, Gilbert, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.