The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Jan. 09, 2023
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hao-Cheng Hou, Hsinchu, TW;
Tsung-Ding Wang, Tainan, TW;
Jung Wei Cheng, Hsinchu, TW;
Yu-Min Liang, Zhongli City, TW;
Chien-Hsun Lee, Chu-tung Town, TW;
Shang-Yun Hou, Jubei City, TW;
Wei-Yu Chen, Hsinchu, TW;
Collin Jordon Fleshman, Hsinchu, TW;
Kuo-Lung Pan, Hsinchu, TW;
Shu-Rong Chun, Hsinchu, TW;
Sheng-Chi Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.