The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

May. 16, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Geng-Ming Chang, Taichung City, TW;

Chih-Hang Tung, Hsinchu, TW;

Chen-Hua Yu, Hsinchu City, TW;

Kuo-Chung Yee, Taoyuan City, TW;

Kewei Zuo, Xinbei City, TW;

Shou-Yi Wang, Hsinchu City, TW;

Tzu-Cheng Lin, Hsinchu City, TW;

Shih-Wei Liang, Taichung City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 46/00 (2026.01); H10W 90/00 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 42/121 (2026.01); H10W 46/00 (2026.01); H10W 90/00 (2026.01); H10W 46/301 (2026.01); H10W 72/985 (2026.01); H10W 80/163 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/792 (2026.01);
Abstract

A method for forming a semiconductor device is provided. The method includes forming first bonding features and a first alignment mark including first patterns in a top die and forming second bonding features and a second alignment mark in a bottom wafer. The method also includes determining a first benchmark and a second benchmark. The method further includes aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, at least two of the first patterns are oriented along a first direction, and at least two of the first patterns are oriented along a second direction that is different from the first direction. The top die is aligned with the bottom wafer by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with the first direction.


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