Xinbei, China

Kewei Zuo

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kewei Zuo. Retrieved from https://idiyas.com/inventor/kewei-zuo-73cmddqb

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Kewei Zuo - Innovator in Semiconductor Technology

Introduction

Kewei Zuo is an inventor based in Xinbei, China. He has made significant contributions to the field of semiconductor technology. Although he currently holds no granted patents, his innovative ideas are reflected in his latest patent applications.

Latest Patent Applications

1. **PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME** - This application describes a package structure that includes a first bonding film on a first package component and a first alignment mark in the first bonding film. The first alignment mark consists of a plurality of first patterns spaced apart from each other. Additionally, the package structure includes a second bonding film on a second package component, bonded to the first bonding film, and a second alignment mark in the second bonding film. The second alignment mark also includes a plurality of second patterns spaced apart from each other, with the first patterns overlapping the second patterns. This design allows for the formation of an interference pattern by the optical signal passing through the varying spacing between the gratings of the top wafer and bottom wafer, improving the resolution of overlay measurement.

2. **SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME** - This application outlines a method for forming a semiconductor device. The method includes forming first bonding features and a first alignment mark with first patterns in a top die, as well as forming second bonding features and a second alignment mark in a bottom wafer. The process involves determining a first benchmark and a second benchmark, and aligning the top die with the bottom wafer using the first and second alignment marks. The alignment is achieved by adjusting a virtual axis to be substantially parallel with the first direction of the first patterns.

Conclusion

Kewei Zuo is an innovative inventor whose work in semiconductor technology showcases his potential in the field. His latest patent applications reflect his commitment to advancing technology, even in the absence of granted patents.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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