The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Sep. 29, 2023
Intel Corporation, Santa Clara, CA (US);
Debendra Mallik, Chandler, AZ (US);
Robert L Sankman, Phoenix, AZ (US);
Robert Nickerson, Chandler, AZ (US);
Mitul Modi, Phoenix, AZ (US);
Sanka Ganesan, Chandler, AZ (US);
Rajasekaran Swaminathan, Chandler, AZ (US);
Omkar Karhade, Chandler, AZ (US);
Shawna M. Liff, Scottsdale, AZ (US);
Amruthavalli Alur, Tempe, AZ (US);
Sri Chaitra J. Chavali, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.