The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Jul. 09, 2021
Applicants:

Zhuhai Access Semiconductor Co., Ltd., Guangdong, CN;

Nexperia B.v., Nijmegen, NL;

Inventors:

Xianming Chen, Guangdong, CN;

Frank Burmeister, Guangdong, CN;

Lei Feng, Guangdong, CN;

Yujun Zhao, Guangdong, CN;

Benxia Huang, Guangdong, CN;

Jinxin Yi, Guangdong, CN;

Jindong Feng, Guangdong, CN;

Yuan Li, Guangdong, CN;

Lina Jiang, Guangdong, CN;

Edward Tena, Guangdong, CN;

Wenshi Wang, Guangdong, CN;

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H05K 3/18 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/4828 (2013.01); H01L 21/4871 (2013.01); H01L 21/76871 (2013.01); H01L 23/49894 (2013.01); H05K 3/181 (2013.01); H05K 3/3452 (2013.01);
Abstract

A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.


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