The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2025
Filed:
Sep. 25, 2020
Intel Corporation, Santa Clara, CA (US);
Gilbert Dewey, Beaverton, OR (US);
Nazila Haratipour, Hillsboro, OR (US);
Siddharth Chouksey, Portland, OR (US);
Arnab Sen Gupta, Hillsboro, OR (US);
Christopher J. Jezewski, Portland, OR (US);
I-Cheng Tung, Hillsboro, OR (US);
Matthew V. Metz, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Intel Coporation, Santa Clara, CA (US);
Abstract
Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.