The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2025
Filed:
Jul. 23, 2020
Shanghai Ic R&d Center Co., Ltd., Shanghai, CN;
Xueru Yu, Shanghai, CN;
Hongxia Sun, Shanghai, CN;
Chen Li, Shanghai, CN;
Pengfei Wang, Shanghai, CN;
Jiebin Duan, Shanghai, CN;
Xiucui Wang, Shanghai, CN;
Hao Fu, Shanghai, CN;
Tao Zhou, Shanghai, CN;
Yan Yan, Shanghai, CN;
Bowen Xu, Shanghai, SH;
Lingyi Guo, Shanghai, CN;
Liren Li, Shanghai, CN;
SHANGHAI IC R&D CENTER CO., LTD., Shanghai, CN;
Abstract
The present invention disclosures a critical dimension error analysis method, comprising: S: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S: removing extreme outliers from the critical dimension (CD) values; S: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD″) values, according to relative error between CD″ and CD, dividing the rebuilt critical dimension (CD″) values into scenes and the number of the scenes is A; S: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S: modifying machine parameters and masks by the correction model according to above calculation results. The present invention uses an outer limit to remove extreme outliers, so as to analyze a critical dimension error during a lithography process quickly and accurately.