The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2025
Filed:
Aug. 04, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ting-Ya Lo, Hsinchu, TW;
Cheng-Chin Lee, Taipei, TW;
Shao-Kuan Lee, Kaohsiung, TW;
Chi-Lin Teng, Taichung, TW;
Hsin-Yen Huang, New Taipei, TW;
Hsiaokang Chang, Hsinchu, TW;
Shau-Lin Shue, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions. The method includes forming a capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the first conductive layer, forming a sacrificial layer in the one or more openings, recessing the sacrificial layer, forming a support layer on the recessed sacrificial layer in each of the one or more openings, removing the sacrificial layer to form an air gap in each of the one or more openings, forming a dielectric fill on the support layer, replacing the first conductive layer in the one or more openings with a second conductive layer, selectively forming a two-dimensional (2D) material layer on the second conductive layer, forming a first etch stop layer on the dielectric fill and the support layer, forming a second etch stop layer on the first etch stop layer and the 2D material layer, forming a dielectric material on the second etch stop layer, forming a contact opening through the dielectric material, the second etch stop layer, and the 2D material layer to expose a top surface of the second conductive layer, and forming a first conductive feature in the contact opening.