The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Oct. 25, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek A. Sharma, Hillsboro, OR (US);

Van H. Le, Beaverton, OR (US);

Gilbert Dewey, Hillsboro, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Shriram Shivaraman, Hillsboro, OR (US);

Benjamin Chu-Kung, Portland, OR (US);

Yih Wang, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/78642 (2013.01); H01L 21/02647 (2013.01); H01L 29/04 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/42384 (2013.01); H01L 29/6656 (2013.01); H01L 29/6675 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H10B 12/05 (2023.02); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H01L 21/31116 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01);
Abstract

Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.


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