The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2024
Filed:
Mar. 27, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chung-Ming Weng, Hsinchu, TW;
Chen-Hua Yu, Hsinchu, TW;
Chung-Shi Liu, Hsinchu, TW;
Hao-Yi Tsai, Hsinchu, TW;
Cheng-Chieh Hsieh, Tainan, TW;
Hung-Yi Kuo, Taipei, TW;
Tsung-Yuan Yu, Taipei, TW;
Hua-Kuei Lin, Hsinchu, TW;
Hsiu-Jen Lin, Hsinchu, TW;
Ming-Che Ho, Hsinchu County, TW;
Yu-Hsiang Hu, Tainan, TW;
Chewn-Pu Jou, Hsinchu, TW;
Cheng-Tse Tang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.