The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Cheng-Chin Lee, Taipei, TW;

Hsiao-Kang Chang, Hsinchu, TW;

Ting-Ya Lo, Hsinchu, TW;

Chi-Lin Teng, Taichung, TW;

Cherng-Shiaw Tsai, New Taipei, TW;

Shao-Kuan Lee, Kaohsiung, TW;

Kuang-Wei Yang, Hsinchu, TW;

Hsin-Yen Huang, New Taipei, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/76834 (2013.01); H01L 21/76837 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 21/76843 (2013.01); H01L 21/76852 (2013.01); H01L 23/53295 (2013.01);
Abstract

A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.


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