The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2024
Filed:
Jun. 26, 2020
Intel Corporation, Santa Clara, CA (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Arnab Sen Gupta, Beaverton, OR (US);
Travis W. LaJoie, Forest Grove, OR (US);
Sarah Atanasov, Beaverton, OR (US);
Chieh-Jen Ku, Hillsboro, OR (US);
Bernhard Sell, Portland, OR (US);
Noriyuki Sato, Hillsboro, OR (US);
Van Le, Beaverton, OR (US);
Matthew Metz, Portland, OR (US);
Hui Jae Yoo, Hillsboro, OR (US);
Pei-Hua Wang, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.