The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2023
Filed:
Dec. 20, 2019
Intel Corporation, Santa Clara, CA (US);
Nicholas Neal, Gilbert, AZ (US);
Nicholas S. Haehn, Scottsdale, AZ (US);
Je-Young Chang, Tempe, AZ (US);
Kyle Arrington, Gilbert, AZ (US);
Aaron McCann, Queen Creek, AZ (US);
Edvin Cetegen, Chandler, AZ (US);
Ravindranath V. Mahajan, Chandler, AZ (US);
Robert L. Sankman, Phoenix, AZ (US);
Ken P. Hackenberg, Plano, TX (US);
Sergio A. Chan Arguedas, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.