The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Jul. 20, 2021
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Cheng-Hsien Chen, Yunlin County, TW;

Chia-Feng Hsiao, Tainan, TW;

Chung-Hsuan Wu, Tainan, TW;

Chen-Hui Huang, Hsinchu, TW;

Nai-Ying Lo, Kaohsiung, TW;

En-Wei Tsui, Kaohsiung, TW;

Yung-Yu Yang, Tainan, TW;

Chen-Hsuan Hung, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/00 (2017.01); G01N 21/95 (2006.01); G06T 7/13 (2017.01);
U.S. Cl.
CPC ...
G01N 21/9505 (2013.01); G06T 7/0004 (2013.01); G06T 7/13 (2017.01); G06T 2207/30148 (2013.01);
Abstract

A wafer backside defect detection method and a wafer backside defect detection apparatus are provided. The wafer backside defect detection method includes the following steps. A peripheral edge area of a wafer backside image that at least one notch is located is cropped off. Adjacent white pixels on the wafer backside image are connected to obtain a plurality of abnormal regions. If a total area of top N of the abnormal regions is more than 10% of an area of the wafer, it is deemed that the wafer has a roughness defect. N is a natural number. If the total area of the top N of the abnormal regions is less than 1% of the area of the wafer and a largest abnormal region of the abnormal regions is longer than a predetermined length, it is deemed that the wafer has a scratch defect.


Find Patent Forward Citations

Loading…