The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2023
Filed:
Dec. 14, 2016
Intel Corporation, Santa Clara, CA (US);
Sean T. Ma, Portland, OR (US);
Aaron D. Lilak, Beaverton, OR (US);
Justin R. Weber, Portland, OR (US);
Harold W. Kennel, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Gilbert W. Dewey, Beaverton, OR (US);
Cheng-Ying Huang, Portland, OR (US);
Matthew V. Metz, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.