The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Sep. 25, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Justin Weber, Portland, OR (US);

Harold Kennel, Portland, OR (US);

Abhishek Sharma, Portland, OR (US);

Christopher Jezewski, Portland, OR (US);

Matthew V. Metz, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Benjamin Chu-Kung, Portland, OR (US);

Van H. Le, Portland, OR (US);

Arnab Sen Gupta, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/36 (2006.01); H01L 29/22 (2006.01); H01L 29/24 (2006.01); H01L 29/47 (2006.01); H01L 21/322 (2006.01); H01L 29/45 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 29/36 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/322 (2013.01); H01L 21/768 (2013.01); H01L 29/22 (2013.01); H01L 29/2203 (2013.01); H01L 29/24 (2013.01); H01L 29/267 (2013.01); H01L 29/45 (2013.01); H01L 29/47 (2013.01);
Abstract

Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.


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