The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2023
Filed:
Dec. 24, 2014
Intel Corporation, Santa Clara, CA (US);
Sanaz K. Gardner, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Matthew V. Metz, Portland, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Chandra S. Mohapatra, Beaverton, OR (US);
Anand S. Murthy, Portland, OR (US);
Nadia M. Rahhal-Orabi, Hillsboro, OR (US);
Nancy M. Zelick, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.