The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Feb. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aastha Uppal, Chandler, AZ (US);

Omkar Karhade, Chandler, AZ (US);

Ram Viswanath, Phoenix, AZ (US);

Je-Young Chang, Phoenix, AZ (US);

Weihua Tang, Chandler, AZ (US);

Nitin Deshpande, Chandler, AZ (US);

Mitul Modi, Phoenix, AZ (US);

Edvin Cetegen, Chandler, AZ (US);

Sanka Ganesan, Chandler, AZ (US);

Yiqun Bai, Chandler, AZ (US);

Jan Krajniak, Phoenix, AZ (US);

Kumar Singh, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/427 (2006.01); H01L 25/18 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/56 (2013.01); H01L 23/3672 (2013.01); H01L 23/3677 (2013.01); H01L 23/3733 (2013.01); H01L 23/3736 (2013.01); H01L 23/427 (2013.01); H01L 25/18 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01);
Abstract

An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.


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