The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2023
Filed:
Dec. 27, 2017
Intel Corporation, Santa Clara, CA (US);
Gilbert Dewey, Beaverton, OR (US);
Sean T. Ma, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Cheng-Ying Huang, Hillsboro, OR (US);
Anand S. Murthy, Portland, OR (US);
Harold W. Kennel, Portland, OR (US);
Nicholas G. Minutillo, Beaverton, OR (US);
Matthew V. Metz, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.