The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Nov. 13, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shao-Kuan Lee, Kaohsiung, TW;

Hsin-Yen Huang, New Taipei, TW;

Cheng-Chin Lee, Taipei, TW;

Kuang-Wei Yang, Hsinchu, TW;

Ting-Ya Lo, Hsinchu, TW;

Chi-Lin Teng, Taichung, TW;

Hsiao-Kang Chang, Hsinchu, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76816 (2013.01); H01L 23/5329 (2013.01);
Abstract

The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.


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