The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2022
Filed:
Dec. 17, 2018
Intel Corporation, Santa Clara, CA (US);
Kimin Jun, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Willy Rachmady, Beaverton, OR (US);
Aaron Lilak, Beaverton, OR (US);
Brennen Mueller, Portland, OR (US);
Hui Jae Yoo, Portland, OR (US);
Patrick Morrow, Portland, OR (US);
Anh Phan, Beaverton, OR (US);
Cheng-Ying Huang, Hillsboro, OR (US);
Ehren Mannebach, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein describe techniques for a semiconductor device over a semiconductor substrate. A first bonding layer is above the semiconductor substrate. One or more nanowires are formed above the first bonding layer to be a channel layer. A gate electrode is around a nanowire, where the gate electrode is in contact with the first bonding layer and separated from the nanowire by a gate dielectric layer. A source electrode or a drain electrode is in contact with the nanowire, above a bonding area of a second bonding layer, and separated from the gate electrode by a spacer, where the second bonding layer is above and in direct contact with the first bonding layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile