The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2022
Filed:
Jun. 22, 2020
Micron Technology, Inc., Boise, ID (US);
Justin B. Dorhout, Boise, ID (US);
Fei Wang, Boise, ID (US);
Chet E. Carter, Boise, ID (US);
Ian Laboriante, Boise, ID (US);
John D. Hopkins, Meridian, ID (US);
Kunal Shrotri, Boise, ID (US);
Ryan Meyer, Boise, ID (US);
Vinayak Shamanna, Boise, ID (US);
Kunal R. Parekh, Boise, ID (US);
Martin C. Roberts, Boise, ID (US);
Matthew Park, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.