The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2021
Filed:
Dec. 27, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hung-Chun Wang, Taichung, TW;
Chi-Ping Liu, Hsinchu, TW;
Feng-Ju Chang, Hsinchu, TW;
Ching-Hsu Chang, Taipei County, TW;
Wen Hao Liu, Hsinchu County, TW;
Chia-Feng Yeh, Hsinchu, TW;
Ming-Hui Chih, Taipei County, TW;
Cheng Kun Tsai, Hsinchu, TW;
Wei-Chen Chien, Hsinchu, TW;
Wen-Chun Huang, Tainan, TW;
Yu-Po Tang, Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.