The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2020
Filed:
Feb. 15, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Kuan-Yu Huang, Taipei, TW;
Sung-Hui Huang, Dongshan Township, Yilan County, TW;
Shu-Chia Hsu, Hsinchu, TW;
Leu-Jen Chen, Taipei, TW;
Yi-Wei Liu, Taichung, TW;
Shang-Yun Hou, Jubei, TW;
Jui-Hsieh Lai, Taoyuan County, TW;
Tsung-Yu Chen, Hsinchu, TW;
Chien-Yuan Huang, Hsinchu, TW;
Yu-Wei Chen, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.