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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10763426 B1

PDFFull Text
Date of Patent:
Sep. 01, 2020

Filed:

Aug. 27, 2019

Method for forming a flat bottom electrode via (beva) top surface for memory

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hsia-Wei Chen, Taipei, TW;

Chih-Yang Chang, Yuanlin Township, TW;

Chin-Chieh Yang, New Taipei, TW;

Jen-Sheng Yang, Keelung, TW;

Sheng-Hung Shih, Hsinchu, TW;

Tung-Sheng Hsiao, New Taipei, TW;

Wen-Ting Chu, Kaohsiung, TW;

Yu-Wen Liao, New Taipei, TW;

I-Ching Chen, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Changhyun Yi

Int. Cl.
CPC ...
H01L 43/02 (2006.01); H01L 23/538 (2006.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 45/00 (2006.01); H01L 21/768 (2006.01); H01L 27/24 (2006.01); H01L 43/08 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); H01L 21/768 (2013.01); H01L 23/5384 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01L 45/04 (2013.01); H01L 45/1253 (2013.01); H01L 45/16 (2013.01); H01L 45/146 (2013.01);
Abstract

Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

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