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Kaohsiung, Taiwan

Yu-Jung Huang

This inventor holds 9 USPTO granted patents. Top assignee: I-Shou University. Active years: 2014-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Jung Huang. Retrieved from https://idiyas.com/inventor/yu-jung-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9

% Patents Active = 22.2

Average Co-Inventor Count = 2.6

ph-index = 3

Forward Citations = 16(Granted Patents)


Company Filing History:

goldMedal9 out of 107 
 
I-Shou University
 patents

Years Active: 2014-2023

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9 patents (USPTO):Explore Patents
1. 11748545 - Method and electronic device for configuring signal pads between three-dimensional stacked chips (2023-09-05),
2. 10776559 - Defect detection method for multilayer daisy chain structure and system using the same (2020-09-15),
3. 10422831 - Chip-to-chip signal transmission system and signal reception circuit (2019-09-24),
4. 10303823 - Defect detection method for 3D chip and system using the same (2019-05-28),
5. 10063282 - Chip-to-chip signal transmission system and method for arranging chips thereof (2018-08-28),
6. 9374706 - Wireless sensor network and central node device thereof (2016-06-21),
7. 9274167 - Chip-to-chip signal transmission system and chip-to-chip capacitive coupling transmission circuit (2016-03-01),
8. 9060265 - Wireless sensor network and central node device thereof (2015-06-16),
9. 8913687 - Signal transmission system and signal transmission circuit (2014-12-16),

Title: Innovations of Yu-Jung Huang

Introduction

Yu-Jung Huang is a prominent inventor based in Kaohsiung, Taiwan. He has made significant contributions to the field of electronic devices and signal processing, holding a total of nine patents. His work focuses on enhancing the efficiency and reliability of electronic systems.

Latest Patents

One of his latest patents is titled "Method and electronic device for configuring signal pads between three-dimensional stacked chips." This invention provides a method for obtaining frequency response curves corresponding to various parameter sets. It includes selecting a frequency response curve based on the operating frequency and generating a signal pad configuration for chips. Another notable patent is the "Defect detection method for multilayer daisy chain structure and system using the same." This method involves generating physical models with defects, creating training samples, and utilizing machine learning techniques to detect defects in multilayer daisy chain structures.

Career Highlights

Yu-Jung Huang is affiliated with I-Shou University, where he contributes to research and development in electronic engineering. His innovative approaches have garnered attention in the academic and industrial sectors, showcasing his expertise in signal processing and defect detection.

Collaborations

He has collaborated with notable colleagues, including Mei-Hui Guo and Chung-Long Pan, to advance research in their respective fields. Their teamwork has led to the development of cutting-edge technologies and methodologies.

Conclusion

Yu-Jung Huang's contributions to the field of electronics and signal processing are noteworthy. His patents reflect a commitment to innovation and problem-solving in complex electronic systems. His work continues to influence advancements in technology and engineering.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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