Hsinchu, Taiwan

Yu-Hsiang Kao

This inventor holds 5 USPTO granted patents and 2 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2014-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Hsiang Kao. Retrieved from https://idiyas.com/inventor/yu-hsiang-kao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5 

% Patents Active = 80.0

Average Co-Inventor Count = 6.3

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2014-2017

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5 patents (USPTO):Explore Patents

Title: Yu-Hsiang Kao: Innovator in Integrated Circuit Design

Introduction

Yu-Hsiang Kao is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of integrated circuit design, holding a total of 5 patents. His work focuses on optimizing layouts and improving interconnect structures, which are crucial for the advancement of semiconductor technology.

Latest Patents

One of his latest patents is titled "Layout optimization for integrated circuit design." This method involves receiving a target pattern defined by a main pattern, a first cut pattern, and a second cut pattern. A computing system checks the target pattern for compliance with a first constraint associated with the first cut pattern. It also checks for compliance with a second constraint related to the second cut pattern. If a violation of either constraint is found, the computing system modifies the pattern accordingly.

Another notable patent is "Interconnect structure having smaller transition layer via." This invention includes an interconnect structure with a bottom layer over a substrate, featuring at least one bottom layer line and one bottom layer via. Above this, a transition layer is included, which has at least one transition layer line and one transition layer via. The top layer, situated over the transition layer, contains at least one top layer line and one top layer via. Importantly, the transition layer via has a cross-sectional area at least 30% smaller than that of the top layer via.

Career Highlights

Yu-Hsiang Kao is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His innovative work has positioned him as a key player in the development of advanced integrated circuit technologies.

Collaborations

Throughout his career, Yu-Hsiang has collaborated with notable colleagues, including Yuan-Te Hou and Lee-Chung Lu. These partnerships have further enhanced his contributions to the field.

Conclusion

Yu-Hsiang Kao's work in integrated circuit design exemplifies the importance of innovation in technology. His patents reflect a commitment to advancing semiconductor capabilities, making him a significant figure in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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