The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Nov. 24, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Huang-Yu Chen, Zhudong Township, TW;

Yuan-Te Hou, Hsinchu, TW;

Yu-Hsiang Kao, Hsinchu, TW;

Ken-Hsien Hsieh, Taipei, TW;

Ru-Gun Liu, Zhubei, TW;

Lee-Chung Lu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 7/00 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); G03F 7/0035 (2013.01); G06F 17/5072 (2013.01); G06F 2217/08 (2013.01); G06F 2217/12 (2013.01);
Abstract

A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.


Find Patent Forward Citations

Chen, Huang-Yu. (2016). Layout optimization for integrated circuit design (U.S. Patent No. 9292645). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9292645

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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