Tokyo, Japan

Yoshiki Yamamoto

This inventor holds 49 USPTO granted patents and 7 published patent applications, primarily in Semiconductor Devices. Top assignee: Renesas Electronics Corporation. Active years: 2014-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yoshiki Yamamoto. Retrieved from https://idiyas.com/inventor/yoshiki-yamamoto

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 49 

% Patents Active = 100.0

Average Co-Inventor Count = 1.9

ph-index = 5

Forward Citations = 71(Granted Patents)


Location History:

  • Kawasaki, JP (2015)
  • Kanagawa, JP (2015 - 2023)
  • Tokyo, JP (2014 - 2024)

Company Filing History:


Years Active: 2014-2026

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Areas of Expertise:
Semiconductor Device
Manufacturing Method
MISFET
SOI Substrate
Field-Effect Transistor
Buried Oxide
MOSFET
Anti-Fuse Memory
Parasitic Capacitance
Isolation Film
Integrated Circuit
Short-Channel Characteristics
49 patents (USPTO):Explore Patents

Title: **Yoshiki Yamamoto: Pioneering Innovations in Semiconductor Technology**

Introduction

Yoshiki Yamamoto is a renowned inventor based in Tokyo, Japan, with an impressive portfolio of 48 patents to his name. His contributions to the field of semiconductor technology have significantly advanced the capabilities of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, particularly with regard to short-channel characteristics and parasitic capacitance.

Latest Patents

Yamamoto's latest innovations include groundbreaking patents focused on semiconductor devices and methods of manufacturing these devices. One notable patent addresses the occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a Silicon-On-Insulator (SOI) substrate. This invention features a sidewall structure formed by sequentially stacking a silicon oxide film and a nitride film on the gate electrode's sidewall, allowing for enhanced performance and reliability.

Another significant patent outlines a method for manufacturing a semiconductor device where epitaxial layers are selectively formed in the source and drain regions of a MOSFET on an SOI region, while the bulk silicon regions remain free of such layers. By utilizing silicon nitride films to cover the end portions of the epitaxial layers, this technique effectively prevents impurity ions from implanting deeper than intended during the diffusion layer formation.

Career Highlights

Yoshiki Yamamoto's career has been marked by significant advancements in semiconductor technology during his time at Renesas Electronics Corporation. His innovative approaches have helped the company maintain its competitive edge in the rapidly evolving electronics industry. With a focus on research and development, Yamamoto continues to push the boundaries of what is possible in semiconductor design and manufacturing.

Collaborations

Throughout his respected career, Yamamoto has collaborated with fellow researchers and professionals, including Toshiaki Iwamatsu and Hideki Makiyama. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas, further driving advancements in the field of semiconductor technology.

Conclusion

Yoshiki Yamamoto’s dedication to enhancing semiconductor technology has resulted in numerous patents that have transformed the industry. As he continues to work at Renesas Electronics Corporation, his innovative spirit and dedication to research will undoubtedly lead to further breakthroughs, making significant contributions to the world of electronics and technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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