The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Apr. 22, 2024
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yoshiki Yamamoto, Tokyo, JP;

Hideki Makiyama, Tokyo, JP;

Toshiaki Iwamatsu, Tokyo, JP;

Takaaki Tsunomura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 21/82 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1083 (2013.01); H01L 21/265 (2013.01); H01L 21/74 (2013.01); H01L 21/76897 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/0878 (2013.01); H01L 29/41783 (2013.01); H01L 29/4238 (2013.01); H01L 29/66477 (2013.01); H01L 29/665 (2013.01); H01L 29/6653 (2013.01); H01L 29/66537 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66628 (2013.01); H01L 29/66742 (2013.01); H01L 29/66757 (2013.01); H01L 29/66772 (2013.01); H01L 29/6681 (2013.01); H01L 29/7824 (2013.01); H01L 29/7833 (2013.01); H01L 29/78606 (2013.01); H01L 29/78621 (2013.01); H01L 29/78651 (2013.01); H01L 29/78654 (2013.01);
Abstract

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.


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