The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Jun. 11, 2018
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventor:

Yoshiki Yamamoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/266 (2013.01); H01L 21/2652 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 29/0653 (2013.01); H01L 29/1083 (2013.01);
Abstract

A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.


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