The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Mar. 20, 2023
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Yoshiki Yamamoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H10B 10/00 (2023.01); H10D 64/27 (2025.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10D 64/021 (2025.01); H01L 21/02293 (2013.01); H01L 21/76264 (2013.01); H01L 21/76897 (2013.01); H10B 10/12 (2023.02); H10D 64/514 (2025.01); H10D 86/201 (2025.01);
Abstract

A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.


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Yamamoto, Yoshiki. (2026). Semiconductor device and method of manufacturing the same (U.S. Patent No. 12538549). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12538549

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