Yi-Lin Chuang

This inventor holds 50 USPTO granted patents and 5 published patent applications, primarily in Integrated Circuit Design. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., TSMC Nanjing Company, Limited. Active years: 2014-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yi-Lin Chuang. Retrieved from https://idiyas.com/inventor/yi-lin-chuang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 50 (Patent Applications = 5)

% Patents Active = 86.0

Average Co-Inventor Count = 3.5

ph-index = 6

Forward Citations = 110(Granted Patents)

Location History:

Taipei, TW (2014 - 2024)
Hsinchu, TW (2022 - 2024)

Company Filing History:

50 out of 42,872

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

6 out of 113

TSMC Nanjing Company, Limited

patents

where one patent can have more than one assignee

Years Active: 2014-2026

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Areas of Expertise:

Circuit Synthesis Optimization

Post-Routing Congestion

Design Rule Check

Violation Prediction

Semiconductor Device

Layout Design

Static Voltage Drop

Machine Learning

Inter-Layer Vias

Timing Optimization

Hard-to-Fix Violations

Floor Plan Optimization

50 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12670310 - System and method for diagnosing design rule check violations (2026-06-30),

2. 12340158 - Circuit synthesis optimization for implements on integrated circuit (2025-06-24),

3. 12321682 - Post-routing congestion optimization (2025-06-03),

4. 12299376 - Hard-to-fix (HTF) design rule check (DRC) violations prediction (2025-05-13),

5. 12242788 - Method and system for generating layout design of integrated circuit (2025-03-04),

6. 12216980 - Method and system for fixing violation of layout (2025-02-04),

7. 12154851 - Method of forming a semiconductor device with inter-layer vias (2024-11-26),

8. 12106034 - Rule check violation prediction systems and methods (2024-10-01),

9. 12099793 - Rule check violation prediction systems and methods (2024-09-24),

10. 12039251 - Cell layout of semiconductor device (2024-07-16),

11. 12039249 - System and method for diagnosing design rule check violations (2024-07-16),

12. 12019971 - Static voltage drop (SIR) violation prediction systems and methods (2024-06-25),

13. 11928415 - Hard-to-fix (HTF) design rule check (DRC) violations prediction (2024-03-12),

14. 11900037 - Circuit synthesis optimization for implements on integrated circuit (2024-02-13),

15. 11893334 - Method for optimizing floor plan for an integrated circuit (2024-02-06),

Title: The Innovative Journey of Yi-Lin Chuang

Introduction: Yi-Lin Chuang, a talented inventor hailing from Taipei, Taiwan, has made significant contributions to the world of technology through his groundbreaking innovations.

Latest Patents: Yi-Lin Chuang holds several patents in the field of electronics and telecommunications, with his most recent patent focusing on a revolutionary method for enhancing data transmission speeds in wireless networks.

Career Highlights: With a career spanning over two decades, Yi-Lin Chuang has worked for various tech companies, leading research teams and spearheading projects that have pushed the boundaries of what is possible in the realm of wireless communication.

Collaborations: Throughout his career, Yi-Lin Chuang has collaborated with top engineers, researchers, and scientists from around the globe, fostering a culture of innovation and creativity that has resulted in numerous successful projects and patents.

Conclusion: Yi-Lin Chuang's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and engineers, solidifying his legacy as a true pioneer in the world of electronics and telecommunications.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

5 patents pending: