Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Yi-Lin Chuang

Shih-Yao Lin

Yin-An Chen

Yun-Han Lee

Ching-Fang Chen

Wei-Pin Changchien

Henry Lin

Amos Hong

Huang-Yu Chen

Heng-Yi Lin

Szu-Ju Huang

Ching Lu Hsu

Song Liu

Chin-Her Chien

Jia-Jye Shen

Szu-ju Huang

Shi-Wen Tan

Chih-yuan Stephen Yu

Boh-Yi Huang

Chih-Sheng Hou

Chun-Cheng Ku

Wen-Yuan Fang

Shih Feng Hong

Yung-Chin Hou

Wei-Li Chen

Nan-Hsin Tseng

Ji-Jan Chen

Yu-Chen Huang

Chien-Hui Chen

Chao-Chun Lo

Chin-Hsien Wang

Sandeep Kumar Goel

Chin-Chou Liu

Shao-Yu Wang

Chih-Tien Chang

Kuan-Hua Su

Charles C C Liu

Pei-Pei Chen

Shih Feng Hung

Shih-Feng Hong

Cheng-Pin Chiu

Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Circuit synthesis optimization for implements on integrated circuit

A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Post-routing congestion optimization

A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

Hard-to-fix (HTF) design rule check (DRC) violations prediction

A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.

Method and system for generating layout design of integrated circuit

A method includes the following operations: identifying a layer of a first layout based on a first violation generated on the layer; generating a metal density value associated with the layer; when the metal density value is larger than or equal to a preset value, classifying the first violation into a first class corresponding to routing congestions of the first layout; when the first violation is classified into the first class, assigning, to the first violation, a first operation of a plurality of first pre-stored operations corresponding to the first class; and performing the first operation to the first layout to generate a second layout.

Method and system for fixing violation of layout

A method (of forming a three dimensional integrated circuit (3DIC) structure) includes: forming an interconnection layer including forming a first inter-layer via which connects at a first predetermined location to a first circuit region of a first device layer and which has a footprint that is at least one factor of ten smaller than a footprint of the first circuit region; and forming a first conductive segment in a first metallization layer of a second device layer so as to align with and thereby connect to the first inter-layer via.

Method of forming a semiconductor device with inter-layer vias

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Rule check violation prediction systems and methods

A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

Cell layout of semiconductor device

A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.

System and method for diagnosing design rule check violations

A violation prediction system includes machine learning circuitry trained based on past data to predict the presence of violations in electronic device designs after routing has been performed. The machine learning circuitry configured to predict, based on the past data and a pre-routing layout of an electronic device design, whether one or more violations would be present in in the electronic device design due to routing of the layout.

Static voltage drop (SIR) violation prediction systems and methods

A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.

Method for optimizing floor plan for an integrated circuit

A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

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Taipei, Taiwan

Yi-Lin Chuang