The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Jan. 04, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chao-Chun Lo, Hsinchu, TW;

Boh-Yi Huang, San Jose, CA (US);

Chih-yuan Stephen Yu, San Jose, CA (US);

Yi-Lin Chuang, Taipei, TW;

Chih-Sheng Hou, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/31 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/392 (2020.01); G06F 119/06 (2020.01); G06F 119/08 (2020.01); G06F 119/12 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/337 (2020.01); G06F 30/31 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/392 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01); G06F 2119/12 (2020.01); G06F 2119/18 (2020.01);
Abstract

Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.


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