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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12154851 B1

PDFFull Text
Date of Patent:
Nov. 26, 2024

Filed:

Aug. 20, 2021

Method of forming a semiconductor device with inter-layer vias

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yi-Lin Chuang, Hsinchu, TW;

Ching-Fang Chen, Hsinchu, TW;

Jia-Jye Shen, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Brian Ngo

Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/3947 (2020.01); G06F 30/398 (2020.01); H01L 23/522 (2006.01); G06F 119/12 (2020.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/3947 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01); H01L 23/5286 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method (of forming a three dimensional integrated circuit (3DIC) structure) includes: forming an interconnection layer including forming a first inter-layer via which connects at a first predetermined location to a first circuit region of a first device layer and which has a footprint that is at least one factor of ten smaller than a footprint of the first circuit region; and forming a first conductive segment in a first metallization layer of a second device layer so as to align with and thereby connect to the first inter-layer via.

Find Patent Forward Citations

Chuang, Yi-Lin. (2024). Method of forming a semiconductor device with inter-layer vias (U.S. Patent No. 12154851). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12154851

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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