Hsinchu, Taiwan

Yi-Han Wu

This inventor holds 6 USPTO granted patents and 1 published patent application and 1 EPO patent. Top assignee: Ememory Technology Inc.. Active years: 2021-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yi-Han Wu. Retrieved from https://idiyas.com/inventor/yi-han-wu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6 

% Patents Active = 100.0

 

Average Co-Inventor Count = 5.0

ph-index = 2

Forward Citations = 7(Granted Patents)


Location History:

  • Zhubei, TW (2022)
  • Hsinchu County, TW (2021 - 2023)

Company Filing History:


Years Active: 2021-2025

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6 patents (USPTO):Explore Patents

Title: Innovations by Yi-Han Wu

Introduction

Yi-Han Wu is a prominent inventor based in Hsinchu County, Taiwan. He has made significant contributions to the field of electronics, particularly in the development of electrostatic discharge (ESD) protection circuits. With a total of 6 patents to his name, Wu's work has been instrumental in enhancing the reliability of electronic devices.

Latest Patents

One of Yi-Han Wu's latest patents is an electrostatic discharge circuit. This innovative ESD circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first ESD current path, a second ESD current path, a biasing circuit, and a control circuit. The control circuit is connected between the pad and a first node, while the first P-type transistor is connected with the pad, the control circuit, and a second node. The first and second ESD current paths are connected between the second node and the first node. Additionally, the second P-type transistor is connected with the pad, the control circuit, and a third node, and the biasing circuit is connected between the third node and the first node. The third P-type transistor is connected with the pad, the third node, and a fourth node, with the internal circuit connected between the fourth node and the first node.

Another notable patent is an integrated circuit with the capability of inhibiting ESD zap. This integrated circuit features an ESD inhibition circuit connected with a first pad, a first node, and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector, and a switching transistor. The capacitor bank is connected between the first pad and a third node, while the resistor is connected between the third node and the first node. The voltage selector's input terminals are connected with the third node and a fourth node, respectively, and its output terminal is connected with a fifth node. The switching transistor has its first terminal connected with the first pad and its second terminal connected with the second node, with the gate terminal connected with the fifth node.

Career Highlights

Yi-Han Wu is currently employed at Ememory Technology Inc., where he continues to innovate in the field of electronic circuit design. His work has garnered attention for its practical applications in protecting sensitive electronic components from ESD damage.

Collaborations

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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