The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Mar. 04, 2020
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Yun-Jen Ting, Hsinchu County, TW;

Chih-Wei Lai, Hsinchu County, TW;

Yi-Han Wu, Hsinchu County, TW;

Kun-Hsin Lin, Hsinchu County, TW;

Hsin-Kun Hsu, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/28 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H02M 1/14 (2006.01); H02M 3/07 (2006.01); H01L 23/60 (2006.01); H01L 23/62 (2006.01); H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0274 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 23/60 (2013.01); H01L 23/62 (2013.01); H01L 27/0248 (2013.01); H01L 27/0251 (2013.01); H01L 27/0255 (2013.01); H01L 27/0266 (2013.01); H01L 27/0285 (2013.01); H01L 27/0288 (2013.01); H01L 29/40114 (2019.08); H01L 29/456 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H02H 9/046 (2013.01); H02M 1/14 (2013.01); H02M 3/07 (2013.01);
Abstract

An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.


Find Patent Forward Citations

Ting, Yun-Jen. (2022). Electrostatic discharge circuit (U.S. Patent No. 11508719). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11508719

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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