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For the Inventor, By the Inventor

Cupertino, CA, United States of America

Yao Tung Yen

This inventor holds 11 USPTO granted patents. Top assignees: Pericom Semiconductor Corporation, Intel Corporation, Hewlett-Packard Company. Active years: 1978-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yao Tung Yen. Retrieved from https://idiyas.com/inventor/yao-tung-yen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 11

% Patents Active = 54.5

Average Co-Inventor Count = 1.1

ph-index = 10

Forward Citations = 223(Granted Patents)


Company Filing History:

goldMedal8 out of 138 
 
Pericom Semiconductor Corporation
 patents
silverMedal2 out of 56,365 
 
Intel Corporation
 patents
bronzeMedal1 out of 9,639 
 
Hewlett-Packard Company
 patents
4. 1 out of 1 
 
Transcomputer, Inc.
 patent
where one patent can have more than one assignee

Years Active: 1978-2006

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11 patents (USPTO):Explore Patents
1. 7126829 - Adapter board for stacking Ball-Grid-Array (BGA) chips (2006-10-24),
2. 7068064 - Memory module with dynamic termination using bus switches timed by memory clock and chip select (2006-06-27),
3. 7020208 - Differential clock signals encoded with data (2006-03-28),
4. 6947304 - DDR memory modules with input buffers driving split traces with trace-impedance matching at trace junctions (2005-09-20),
5. 6927992 - Trace-impedance matching at junctions of multi-load signal traces to eliminate termination (2005-08-09),
6. 6686763 - Near-zero propagation-delay active-terminator using transmission gate (2004-02-03),
7. 6501307 - Spread-spectrum clock buffer/driver that modulates clock period by switching loads (2002-12-31),
8. 5808502 - Parallel micro-relay bus switch for computer network communication with (1998-09-15),
9. 5061989 - Mechanical translator for semiconductor chips (1991-10-29),
10. 4195258 - Logic analyzer for integrated circuits, microcomputers, and the like (1980-03-25),
11. 4084869 - Interconnector for integrated circuit package (1978-04-18),

Title: Yao Tung Yen: Innovator in Electronic Device Technology

Introduction

Yao Tung Yen is a prominent inventor based in Cupertino, California, known for his significant contributions to electronic device technology. With a total of 11 patents to his name, Yen has made remarkable advancements in the field of electronics, particularly in the design and functionality of memory modules and adapter boards.

Latest Patents

Yen's latest patents include an innovative adapter board for stacking Ball-Grid-Array (BGA) chips. This technology allows electronic devices packaged with arrayed solder balls, leads, or pads to be stacked together efficiently. Each stack features a bottom adapter card with metal contacts that align with the solder balls of a lower BGA package, ensuring seamless connectivity to an underlying motherboard or printed-circuit board (PCB). Another notable patent is for a memory module with dynamic termination using bus switches timed by memory clock and chip select. This low-power memory module incorporates an active termination circuit at each end of critical signal traces, enhancing performance and efficiency.

Career Highlights

Throughout his career, Yao Tung Yen has worked with leading companies in the technology sector, including Pericom Semiconductor Corporation and Intel Corporation. His experience in these organizations has allowed him to develop cutting-edge technologies that have had a lasting impact on the industry.

Collaborations

Yen has collaborated with notable professionals in the field, including Alex Chi-Ming Hui and En-Ling Feng. These partnerships have contributed to the successful development of his innovative technologies.

Conclusion

Yao Tung Yen's contributions to electronic device technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence advancements in electronic design and functionality.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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