Ddr memory modules with input buffers driving split traces with trace-impedance matching at trace junctions

Abstract

A memory module has improved signal propagation delays for signals externally driven such as from a motherboard. Reflections from junctions of wiring traces on the memory module are reduced or eliminated. An input buffer or register receives a signal from the motherboard and splits the signal to drive two outputs to two separate traces. Each trace is enlarged in width or thickness, such as by using a double-width wiring trace. At the fare end of each double-width trace, a junction is made to two minimum-width traces that connect to small stub traces to DRAM inputs. Reflections from the junction are eliminated or reduced by trace-impedance matching, since the input impedance of the double-width trace from the input buffer is about the same as the combined impedance of the two minimum-width traces. Trace-input matching and input buffering can improve signal integrity and overall propagation delay.