logo

For the Inventor, By the Inventor

Hangzhou, China

Xiaochun Tan

USPTO Granted Patents = 26 

Average Co-Inventor Count = 1.1

ph-index = 4

Forward Citations = 52(Granted Patents)


Location History:

  • Hangzhou, CH (2015)
  • ZheJiang Province, CN (2016)
  • Zhejiang, CN (2016)
  • Hangzhou, CN (2014 - 2022)

Company Filing History:

goldMedal26 out of 626 
 
Silergy Semiconductor Technology (hangzhou) Ltd
 patents

Years Active: 2014-2025

Loading Chart...
26 patents (USPTO):Explore Patents
1. 12418000 - Stacked package structure and stacked packaging method for chip (2025-09-16),
2. 11462510 - Stacked package structure and stacked packaging method for chip (2022-10-04),
3. 10763241 - Stacked package structure and stacked packaging method for chip (2020-09-01),
4. 10741481 - Integrated package assembly for switching regulator (2020-08-11),
5. 10734249 - Package structure and method thereof (2020-08-04),
6. 10319608 - Package structure and method therof (2019-06-11),
7. 10128221 - Package assembly having interconnect for stacked electronic devices and method for manufacturing the same (2018-11-13),
8. 10043738 - Integrated package assembly for switching regulator (2018-08-07),
9. 9786521 - Chip package method for reducing chip leakage current (2017-10-10),
10. 9780081 - Chip package structure and manufacturing method therefor (2017-10-03),
11. 9735122 - Flip chip package structure and fabrication process thereof (2017-08-15),
12. 9699918 - Package assembly and method for manufacturing the same (2017-07-04),
13. 9653355 - Flip chip package structure and fabrication process thereof (2017-05-16),
14. 9595453 - Chip package method and package assembly (2017-03-14),
15. 9373567 - Lead frame, manufacture method and package structure thereof (2016-06-21),

Title: Innovator Spotlight: Xiaochun Tan and His Contributions to Semiconductor Packaging

Introduction: Xiaochun Tan is a prominent inventor from Hangzhou, China, recognized for his substantial contributions to the field of semiconductor technology. With a remarkable portfolio of 25 patents, he has played a pivotal role in developing innovative packaging solutions that enhance the efficiency and functionality of electronic devices.

Latest Patents: Among his latest contributions, Xiaochun Tan has designed a unique stacked package structure for chips. This patent outlines a sophisticated stacked package structure that integrates a substrate featuring two surfaces, a first die with defined active and back faces, and a first enclosure serving as a protective cover. The innovation includes an interlinkage that connects to the first enclosure for effective electrical coupling, a first redistribution body that partially exposes outer pins for external circuitry connection, and a penetrating body extending through the first enclosure and substrate. Furthermore, his design incorporates a second die with electrodes that are electrically linked to the penetrating body, showcasing a comprehensive approach to enhancing chip packaging technologies.

Career Highlights: Tan is currently employed at Silergy Semiconductor Technology (Hangzhou) Ltd., where he continues to push the boundaries of semiconductor innovations. His expertise and creative solutions have established him as a leading figure in the semiconductor packaging arena.

Collaborations: Xiaochun Tan's innovative journey is further supported by his collaborations with talented colleagues such as Jiaming Ye and Wei P Chen. Together, they contribute to advancing technology and improving semiconductor packaging methodologies, fostering a dynamic work environment that encourages creativity and invention.

Conclusion: Xiaochun Tan's dedication to innovation is evident through his extensive patent portfolio and his work at Silergy Semiconductor Technology (Hangzhou) Ltd. He continues to be a driving force in the field, shaping the future of semiconductor packaging with impactful inventions that address the industry's evolving needs.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…