The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Jun. 10, 2016
Applicant:

Silergy Semiconductor Technology (Hangzhou) Ltd., Hangzhou, CN;

Inventors:

Xiaochun Tan, Hangzhou, CN;

Jiaming Ye, Hangzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4832 (2013.01); H01L 21/4825 (2013.01); H01L 21/4842 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49541 (2013.01); H01L 23/49582 (2013.01);
Abstract

The present disclosure relates to a chip package method and a package assembly. A metal plate is micro-etched to form trenches having a predetermined depth. A metallic conductor is formed as a leadframe by filling the trenches with a material having relatively small adhesion with the metal plate. In such manner, the metal plate can be peeled off from a package body after the chip is electrically coupled to the metallic conductor and encapsulated by a molding process. A bottom of the metallic conductor is exposed from the package body. A chip package is thus completed. It simplifies a manufacture process for forming a chip package, reduces manufacture cost, and increases reliability of the chip package.


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