San Jose, CA, United States of America

Wei-Yu Chen

This inventor holds 36 USPTO granted patents and 10 published patent applications, primarily in Graphics Processing. Top assignees: Intel Corporation, Hon Hai Precision Industry Co., Ltd.. Active years: 2011-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Wei-Yu Chen. Retrieved from https://idiyas.com/inventor/wei-yu-chen-4ijj2i4c

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 36 

% Patents Active = 77.8

Average Co-Inventor Count = 4.6

ph-index = 3

Forward Citations = 42(Granted Patents)


Location History:

  • El Cerrito, CA (US) (2011 - 2013)
  • Santa Clara, CA (US) (2012 - 2020)
  • San Jose, CA (US) (2019 - 2024)

Company Filing History:


Years Active: 2011-2025

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Areas of Expertise:
Register Allocation
Instruction Prefetching
Bank Conflict Reduction
Systolic Array
SIMD Environment
Secure Hash Algorithm
Graphics Environment
Thread Management
Three Dimensional Printing
Software Transactional Memory
Graphics Data Prefetching
Multithreaded Application
36 patents (USPTO):Explore Patents

Title: **Innovative Contributions of Wei-Yu Chen in Patent Engineering**

Introduction

Wei-Yu Chen is a prolific inventor based in San Jose, California, known for his innovative contributions to technology with a remarkable portfolio of 32 patents. His work primarily focuses on enhancing processing efficiency and optimizing resource allocation within computing systems.

Latest Patents

Two of his latest patents illustrate the advanced technology he has developed:

1. **Multiple Register Allocation Sizes for Threads** - This patent describes a system featuring one or more processors, including a graphics processor that possesses a first local thread dispatcher and multiple processing resources. The invention allows the processors to determine suitable register sizes for threads, ensuring that they can effectively utilize available processing resources to allocate registers efficiently. This optimization can significantly enhance the performance of multi-threaded applications.

2. **Systolic Array of Arbitrary Physical and Logical Depth** - This patent focuses on a processing apparatus that includes a general-purpose parallel processing engine and a matrix accelerator. It introduces innovative circuitry designed to perform operations linked to instructions with a flexible depth configuration. The technology allows for reading operands from a dedicated register file, performing operations through angled pipelines, and writing outputs back to the register file, thereby improving computational efficiency.

Career Highlights

Wei-Yu Chen has made significant strides in the tech industry, having worked at reputable companies such as Intel Corporation and Hon Hai Precision Industry Co., Ltd. His tenure at these organizations has equipped him with extensive experience in cutting-edge technology and innovation.

Collaborations

Throughout his career, Wei-Yu Chen has collaborated with esteemed colleagues including Guei-Yuan Lueh and Subramaniam M. Maiyuran. These collaborations have undoubtedly influenced his work and contributed to the successful development of his patents.

Conclusion

Wei-Yu Chen stands as a quintessential figure in the realm of technological innovation. His extensive patent portfolio reflects his commitment to advancing computer processing methodologies and resource management. With a track record of impactful inventions, he continues to pave the way for future developments in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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