The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Supratim Pal, Folsom, CA (US);

Wajdi Feghali, Boston, MA (US);

Changwon Rhee, Rocklin, CA (US);

Wei-Yu Chen, San Jose, CA (US);

Timothy R. Bauer, Hillsboro, OR (US);

Alexander Lyashevsky, Cupertino, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06T 15/00 (2011.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
H04L 9/0643 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/3836 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06T 15/005 (2013.01);
Abstract

An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.


Find Patent Forward Citations

Loading…